adder

module test_adder1;

 reg a,b;
 reg carry_in ;
 wire sum;
 wire carry_out;

 adder1_behavorial A1(carry_out, sum, a, b, carry_in);

 initial
  begin
    carry_in = 0; a = 0; b = 0;
    # 100 if ( carry_out !== 0 | sum !== 0)
                $display(" 0+0+0=00 sum is WRONG!");
              else
                $display(" 0+0+0=00 sum is RIGHT!");
    carry_in = 0; a = 0; b = 1;
    # 100 if ( carry_out !== 0 | sum !== 1)
               $display(" 0+0+1=01 sum is WRONG!");
              else
               $display(" 0+0+1=01 sum is RIGHT!");
    carry_in = 0; a = 0; b = 1;
    # 100 if ( carry_out !== 0 | sum !== 1)
               $display(" 0+1+0=01 sum is WRONG!");
              else
               $display(" 0+1+0=01 sum is RIGHT!");
    carry_in = 1; a = 1; b = 0;
    # 100 if ( carry_out !== 1 | sum !== 0)
                $display(" 0+1+1=10 sum is WRONG!");
              else
                $display(" 0+1+1=10 sum is RIGHT!");
    carry_in = 0; a = 0; b = 1;
    # 100 if ( carry_out !== 0 | sum !== 1)
               $display(" 1+0+0=01 sum is WRONG!");
              else
               $display(" 1+0+0=01 sum is RIGHT!");
    carry_in = 1; a = 1; b = 0;
    # 100 if ( carry_out !== 1 | sum !== 0)
               $display(" 1+0+1=10 sum is WRONG!");
              else
               $display(" 1+0+1=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 0;
    # 100 if ( carry_out !== 1 | sum !== 0)
               $display(" 1+1+0=10 sum is WRONG!");
              else
               $display(" 1+1+0=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 1;
    # 100 if ( carry_out !== 1 | sum !== 1)
               $display(" 1+1+1=11 sum is WRONG!");
              else
               $display(" 1+1+1=11 sum is RIGHT!");

    $finish;
  end
endmodule



module adder1_behavorial (carry_out, sum, a, b, carry_in);
 input a, b, carry_in;
 output carry_out, sum;
  assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)(a&b&carry_in)(~a&~b&carry_in)
  assign carry_out = a&carry_in|a&b|b&carry_in;
endmodule

三位元多工器 結構模式

module top;

wire [2:0]A,B,OUT;
wire SEL;
system_clock #12800 clock1(A[0]);
system_clock #6400 clock2(A[1]);
system_clock #3200 clock3(A[2]);
system_clock #1600 clock4(B[0]);
system_clock #800 clock5(B[1]);
system_clock #400 clock6(B[2]);
system_clock #200 clock7(SEL);
mux3 M1(OUT, A, B, SEL);
endmodule

module mux(OUT, A, B, SEL);
output OUT;
input A,B,SEL;
not I5 (sel_n, SEL);
and I6 (sel_a, A, SEL);
and I7 (sel_b, sel_n, B);
or I4 (OUT, sel_a, sel_b);
endmodule

module mux2(OUT, A, B, SEL);
output [1:0] OUT;
input [1:0] A,B;
input SEL;
mux hi (OUT[1], A[1], B[1], SEL);
mux lo (OUT[0], A[0], B[0], SEL);
endmodule

module mux3(OUT, A, B, SEL);
output [2:0] OUT;
input [2:0] A,B;
input SEL;
mux hi    (OUT[2], A[2], B[2], SEL);
mux middle(OUT[1], A[1], B[1], SEL);
mux lo    (OUT[0], A[0], B[0], SEL);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>2000)$stop;

endmodule